Scott Stites KLEE 2 Sequencer
This page is dedicated to the KLEE2 i plan to build. It's a supercool project and there is even a set of PCBs available soon. Check out the electro-music forum for further information:
This project is still in progress so schematics and/or frontpanel design may be amended as long as you see this words! You can build it the way the current schematics suggest.
The following schematics are from scott stites revision 3 and offer different scaler and output options to choose from.
Looking at the schematic, one can see now where the Switch n, RClock, PSA, and R Async signals go. Each RClock pulse causes the contents of the registers to shift right. When PSA goes high, the CD4034 now is aware its parallel input pins are even there. While the CD4034 is looking at its parallel pins, R Async sneaks in, gives it a poke in the whiskers, and now the CD4034 outputs (the 'B' side) have the same bit configuration as its inputs (the 'A' side the 'Switch n' inputs are connected to). PSA then goes low, and RClock is free to start shifting things right (or down, as it appears on the schematic). The outputs of each CD4034 go to two different destinations. The 'Stage n' outputs (Stage 1, Stage 2, etc.) serve to activate CD4066 sections that feed a selectable voltage to the step pots themselves. The LEDs obviously are the LEDs one normally associates with any sequencer - they indicate which stages are active.
Getting back to the CD4034s, you'll notice that the last ouput of U1 (B8, pin 1) is fed to the serial input of the second CD4034 (pin 10 SDI). This provides the bridge so that bit 8 can 'walk across' and become bit 9 when the RClock pulse says 'shift right'.
This brings us to a vital function of the original Klee. Notice that the last output of CD4034 U2 doesn't simply loop back to the serial input of the first CD4034, U1. Instead, it goes to a switch that will allow this to happen if you want it to. The Pattern/Random switch SW1, when set to 'Pattern', will allow the 16 bit pattern you programmed in the last chapter to loop around forever and ever. However, when SW1 is in the 'Random' position, it allows something very different to happen.
I bet you guessed a random function, right? Yes. This is the portion of the circuit I nearly excluded because of my infatuation with looping patterns, which is certainly fun and predictable, if anything about Klee sequencing can be called predictable. But Uncle K's musing about stones inclined me to go ahead and put it on the breadboard, and I found I'd forgotten just how spiffy this function can be.
The Random function lets chance become the pattern programmer. Chance, as it turns out, has no restriction to how many bits the pattern is, or what order, or if it ever repeats in this lifetime.
Enter our faithful comparator, U3. There are two inputs to the comparator. One input is a variable voltage, set by the Reference Level pot. The other input is an externally applied signal, the level of which is controlled by the Random Input Level pot.
If the signal applied to pin 5 of U3, through the Random Input Level pot, exceeds the level set by the Reference Level pot, then the output of the comparator will be high. Otherwise, it will be low.
The signal applied to the random input connector can be any signal commonly found on a synthesizer - an LFO, a VCO, noise, sample and hold - anything that goes above ground in level.
The output of the comparator goes to two destinations. One is the 'Ref' LED, which lights whenever the comparator goes high. The other destination is the Random/Pattern switch.
If the Random/Pattern switch is set to 'Random' then the output of the comparator is funneled to the serial input of the first CD4034. When R Clock pulses to shift the register right, the instantaneous high or low value of the comparator is programmed as the first bit in the register. In other words, if the comparator happens to be high at the time, bit 1 is made high. If the comparator happens to be low at the time, bit 1 is made low. If it happens to be in between high or low, well, let the CMOS Gods sort it out. After all, it is a random function.
On the other end of the Shift Register, the last bit on U2, B8, jumps off the cliff and falls screaming into the void, never to be heard from again when RClock wields its deadly pulse.
So, using an external input, adjusting its level and adjusting the reference level can produce anything from intermittent bits, bursts of bits, or evenly distributed random bits. In a way, the reference control can be thought of as a 'probability of change' control. It could be modified to accept an external voltage to randomize it even further, though running the signal input through a VCA will do the same thing. The Ref LED is a good indicator that you're in the ball park. If it's not lit at all, your register becomes successively filled up with 0s with every pulse of RClock. If it's constantly on, the register fills up with 1's. If it's flickering, then things start to randomize pretty well. Note, it can appear to be on more than it's off, but one can still get a large amount of 0's. The LED is flickering faster than the eye can see. If it happens to flicker low for that .06 microseconds that the CD4034 will even consider it as a bit candidate, then bit 1 will be low.
The selected signal input makes just as much difference in the flavor of the random pattern sequence as the settings of the level control and reference pot. LFO's will be cyclical in their randomization. VCO's can be cyclical as well, depending on their relation to the clock frequency (a factor as yet unmentioned in the generation of random patterns). Noise generally produces the most evenly distributed random patterns. It was the noise generator of my DSC2000 that produced the frogskin bikini pattern.
Note that the load function is still active even in random mode. This can be taken advantage of to create half programmed/half random patterns through judicious selection of the reload switch on Bus 1, something to be explained in a later installment.

Paul Klee:
Der Paukenspieler
scaler v1?scaler v2?scaler v3?
cv output v1gate bus?cv output v2
cv output v3
merge function off for both busses
one bit active in register
merge function on for both busses
one bit active in register
It will look like this.
his site...frontpanel designconstructionschematics
know the klee (manual)Glossary (mnemonic table)?schematics rev 3
Synth DIY
last update 16 SEP 08